1. Field of the Invention
The invention relates to a device for the processing of digital signals by means of combinatorial and sequential logic elements, it being possible to form a first shift register from said sequential elements for the testing of the device, said shift register comprising a first series input, a first series output, a first parallel output for applying a data pattern stored to further elements of the circuit for processing, and a first parallel input for subsequently receiving a result pattern of said processing, a test pattern generator being connected to said first series input while a verification device is connected to said first series output. In a combinatorial logic element, a change of an input signal may or may not signify a change of an output signal, but independent of the instant at which said change occurs. In a sequential logic element, given memory functions are represented: one or more internal conditions of the element have a given persistence. Depending on the input signals and on the internal condition itself, these conditions cannot always be directly changed (they can be changed, for example, when a next clock pulse period commences, after a given delay, etc).
2. Description of the Prior Art
A device of the described kind is known from an article by M. J. Y. Williams and J. B. Angell, "Enhancing testability of large-scale integrated circuits via test points and additional logic", IEEE, Tr. Computers, Vol. C22, Jan. 1973, pages 46-60. As a result of this technique, the sequential elements of the first shift register can assume a well-defined starting condition. In given cases the complete verification of a long data pattern represents a complex problem; therefore, a result pattern of long length is advantageously converted into a secondary pattern of smaller length. If a deviation occurs in the result pattern, the nature of the fault can in many cases be detected in the circuit. The latter information is not always relevant, for example, when products just finished are tested. In that case the information "good"/"bad" usually suffices and this information is usually still present in the secondary pattern. For the testing of a circuit, often a number of test patterns are used which each produce their own result pattern. The design of such a series of test patterns is a complex matter because the different test patterns preferably serve also to test different sub-functions of the circuit. Furthermore, the evaluation of a large number of result patterns is a time consuming matter. However, the number of test patterns must still be comparatively large in many cases; because if the number is too small, defective circuits will often be accepted erroneously.